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[Udemy 100% Free]-Systemverilog Verification -6: Simulation Regions in Detail


Get 100% Free Udemy Discount Coupon Code ( UDEMY Free Promo Code ) ,You Will Be Able To Enroll this Course “Systemverilog Verification -6: Simulation Regions in Detail” totally FREE For Lifetime Access . Do Hurry Or You Will Have To Pay $ $ .


Be familiar with basics Systemverilog coding Course Duration:  1 Hours

Course Instructor: Brian McCarthy

Language: English

Rating: 5


This Systemverilog course teaches the System-On-Chip design verification used in VLSI industry. It is teaching only a specific topic in SV, the simulation time regions.

While learning SV verification or even after spending years in writing test-benches, it is a hard task for most of the verification engineers to answer anything demanding in depth knowledge in simulation time regions.  Here in this course, this problem is addressed in a simplified manner by explaining every time regions in detail, and connecting different code regions to time regions. You will going through following lectures in this course.

Components of a generic SV design/TB codeIntroduction to Simulation RegionsPreponed RegionActive, Reactive, NBA RegionsObserved RegionsRe-Active, Re-Reactive, Re-NBA RegionsPostponed RegionClass & Functional Coverage Execution Regions

As example explaining advancing simulation through different regions for each time-slot

By taking this course, you will be able to explain what is happening in simulation in each time slot with respect to the code you write. This would be an excellent platform to brush up your SV skills and to address common verification questions confidently.

Who this course is for:
Anyone who does coding in Systemverilog, but have no clear idea about time regions specified in LRM.


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